An Architecture for Exact Arithmetic

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▣ This report is a white paper on the design of the Hensel CPU architecture, introduced for performing exact 2-adic arithmetic at the hardware level with the goal of providing accelerated computing with an alternative to floating-point. The architecture is designed (e.g., with novel arithmetic logic units and processor registers) for performing arithmetic on unique, parsimoniously encoded operands (up to the bit-width of the CPU).  

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2-Adic​ Architecture as a Successor to Floating-Point
 

▣ Floating-point arithmetic requires users to accept tradeoffs between accuracy, performance, and cost. User manuals from companies at the center of the accelerated computing revolution, such as Nvidia and Arm, always warn users of these tradeoffs. SciSci Research and Future Computing view these tradeoffs as obstacles to accelerated computing, which is supposed to offer accuracy and performance to users at a low cost.

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▣ Although modern computing (from the Zuse Z3 to the present) uses floating-point arithmetic, which is based on approximating real numbers with rationals, it has long been known in number theory that p-adic fields offer an alternative (and the only alternative) closure of the rationals whose elements admit unique, exact representations.

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▣ Literature in computer science has explored finite encodings for p-adic numbers and arithmetic algorithms since the 1970's. Nonetheless, these have been devised for implementing exact arithmetic on existing hardware. Hensel endeavors to confront floating-point at its source, which resides at the level of computer architecture.

▣ Unlike software systems such as Magma that offer exact p-adic algorithms to number theorists who understand p-adic numbers, the Hensel CPU is designed to perform 2-adic arithmetic at the machine level, such that operands and outputs can be translated (e.g., symbolically) via higher-level programming languages to users without them having to know anything about p-adic arithmetic. Everyone should benefit from 2-adic arithmetic without having to do it themselves.

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Processor Design for Parallelized, Efficient 2-adic computing

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▣ The Hensel CPU architecture is intended as a load-store architecture, and embodies novel processor design features (e.g., arithmetic logical units and processor registers) for performing 2-adic arithmetic in an optimal and parallelized fashion. The processor is given a nested design, with processor registers encased within nested layers of arithmetic logical units. This design is chosen to best align load-store and parallelized execution with the non-archimedean metric between 2-adic numbers, which, unlike the real number line in the case of ℝ, gives distances between numbers that form a highly nested, non-linear structure, according to which the cluster is designed. Nested clustering design offers two advantages for accelerated computing:

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▣ Clustering: the 2-adic arithmetic logical units (2AALUs) in the Hensel processor, as a cluster, can execute arithmetic in highly parallelized fashion via simultaneous coefficient modification on operands. 

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▣ Nesting: the nested structure of the Hensel processor is designed to utilize non-archimedean properties, such as per-level maximization of 2-adic operand-output distance reduction, to optimize arithmetic and minimize the number of parallel operations needed.

FC Standards for Operand and Instruction Encoding​

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▣ In view of the technical standardization of floating-point arithmetic (e.g., IEEE 754), this report introduces FC 1-2025, a standard for encoding 2-adic numbers. Specifically, FC 1-2025 encodes the coefficients found in 2-adic expansions, which are known to be unique, in a compressed format that does not violate uniqueness. 

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▣ FC-1-2025-encoded operands are stored according to a triple-tree format, which, among other benefits, allows one to avoid using negative indices for coefficients in 2-adic expansions whose summands include those with negative exponents. Non-negativity for indices, for reasons discussed in the report and Appendix, enable the nested 2AALU cluster to maximize per-level efficiency.

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▣ Instructions for parallelized execution are encoded according to a second standard, FC 2-2025.

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​Super-Computing Prospects

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▣ The Hensel CPU is expected to be able to not only execute operations encoded in a FC 2-2025 instruction list in parallel, but execute multiple FC 2-2025 instruction lists themselves in parallel accross the 2AALU cluster.

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▣ The nested design of the Hensel processor, although cumbersome for more elementary applications, is expected to scale rather favorably in the high-performance computing domain. For instance, back-of-the-envelope calculations (with several assumptions) suggest that a nest depth of ≈67 levels is needed for to endow a single Hensel CPU with a zetascale computing capability. 

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Executive Summary