The First Demonstration of Exact Arithmetic

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▣ This report is a white paper on the Virtual Hensel I, a rudimentary emulation of the Hensel CPU architecture developed by SciSci Research and Future Computing. It is to serve as a technical reference to accompany a forthcoming video demonstration of the Virtual Hensel I.  

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Capabilities and Scalability

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▣ The Virtual Hensel I load-store architecture accepts over 50,000 different operands. Each operand has a unique FC-3-2025 encoding, which is decompounded and stored among the 32 processor registers in the Virtual Hensel processor cluster. All 50,000 are within the (5,5,5) encoding ceiling (i.e., their R, L, and T blocks can be of length no more than 5), and were generated algorithmically. Generation of codings under a taller ceiling can be done readily.

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▣ The Virtual Hensel processor is of nest depth 5 (+2), and thus has 32 (i.e., 2^5) processor registers. Operand capacity is expected to scale exponentially with nest depth. The forecasted operand capacity for a Hensel CPU of nest depth 6 (+2) is about 350,000, and 2,400,000 for for 7 (+2). For 15 (+2), it is 18,000,000,000,000.

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▣ The Virtual Hensel can perform as many as 1 billion distinct addition operations and 40,000,000 multiplication operations. (This is based on sampling, reflecting the mean + one standard deviation.)

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▣ Sampling operand pairs whose sum or product is also an operand loadable to the Virtual Hensel within the (5,5,5) encoding ceiling, one finds their distribution, although heterogeneous, to not display any patches, thus suggesting that the exact arithmetic of the Hensel CPU, with operand capacity scaling, should be a general arithmetic capability.

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Novel Features

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▣ The Virtual Hensel visualizes the functionality of the Hensel CPU processor, including the distributed loading of operand χ-IDs to cluster processor registers, and the hop calculus of 2-adic arithmetic unit (2AALU) operations.

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▣ Images of Virtual Hensel visualizations are given to accompany worked examples of exact arithmetic in the report. These worked examples also include full treatment of Hensel arithmetic in the notational conventions developed in the SciSci/Future Computing reports. The reader may appreciate the simplicity with which the Virtual Hensel visualizes processes that are notationally demanding in written form. The forthcoming demonstration video will include animations that dynamically convey the functionality of Hensel arithmetic.

Research Developments​

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▣ Development of the Virtual Hensel involved the establishment of a χ-ID system for load-store, to which the original Hensel report had alluded without concrete discussion. Numerous tricks were devised to encode R, L, and T blocks of FC-1-2025 encodings as χ-IDs in a manner that maximizes the number of operands loadable, in decompounded form, to the 32 Virtual Hensel processor registers, and in a manner that lends itself to easy algorithmic generation of χ-ID encodings. The result is FC-3-2025, an encoding standard for χ-IDs.​​

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▣ The load-store architecture for decompounded loading and recompounded storage of operands using the χ-ID system is discussed in detail.​

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Executive Summary