Starting the Exact Computing Revolution
Future Computing is SciSci's high-performance computing project, established to replace floating-point computing with exact computing.
It's flagship product will be the Hensel CPU, the world's first exact computing CPU.
Timeline
July 2025
Future Computing project begins with the first report on the Hensel CPU, an architecture for exact computing.
August 2025
Technical preview published on the Virtual Hensel I, with an emphasis on processor register loading and operand encoding.
September 2025
Technical reports published on the Hensel CPU's 2-adic arithmetic logic units (2AALUs) and load-store architecture, with emphasis on circuit design and combinational logic of exact arithmetic.
October 2025
Video demo of the Virtual Hensel released, showing exact arithmetic, 2AALU combinatorial logic, and register loading. The Virtual Hensel receives ARIXA assembly input and gives MRIXA machine code output, also introduced in an October technical report.
Invention No. 6
Operand Table
>50,000 Exact Encodings for the Virtual Hensel I
Topics: FC-3-2025 encodings, Virtual Hensel I
Invention No. 4
Arithmetic Logic Units
A circuit-level description of how exact arithmetic is performed
Topics: Combinational logic, circuit design, carry addition, FC-2-2025 instruction computation, scalability, parallelization.
Invention No. 5
RIXA
A RISC Instruction Set Architecture for Exact Computing
Topics: ARIXA assembly language, MRIXA machine code
Invention No. 2
The Virtual Hensel
The first emulation on the Hensel CPU architecture and a proof-of-principle of exact, 2-adic computing
Topics: χ-IDs and χ-address matching for distributed load-store, FC-3-2025 encoding for χ-IDs, loading operations, decompoundment and recompoundment of operands with respect to χ-IDs, algorithmic generation of FC-3-2025 encodings, hop calculus visualization, operand capacity scalability, arithmetic reach scalability, cost-savings of exact computing.
Invention No. 3
Load-Store Architecture
A circuit-level description of how operands are handled in the processor register cluster for efficient, exact arithmetic
Topics: LSU combinational logic, circuit tree design, relationship between χ-modification of operands by LSU loaders and Φ-perturbations of circuit tree paths, relationship to hop calculus and π-sequence passing, parallelization and scaling.
Invention No. 7
Arithmetic Verification
Checking Correctness of Virtual Hensel Arithmetic Logic Units
Topics: Virtual Hensel, FC-3-2025 encodings, 2AALUs, exact arithmetic, verification
Invention No. 1
Hensel CPU
An original computing architecture design for doing exact arithmetic, rather than floating-point
Topics: 2-adic expansions, FC 1-2025 standard for encoding 2-adic expansion coefficients, processor architecture, 2-adic arithmetic logical units (2AALUs), FC 2-2025 parallelized instruction standard, arithmetic parallelization, optimality of parallelization with respect to non-Archimedean distance, error-detection and fault-tolerance, supercomputing (i.e., zetascale) prospects and a exact operations per second (XOPS) benchmark.
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