Building the First Errorless CPU
SciSci Research is building the first errorless CPU, capable of perfect-precision exact arithmetic, without rounding errors, in order to end the tradeoff between precision and speed in AI compute.
How the Errorless CPU Began
SciSci Research began developing the errorless CPU with its "Future Computing" project, which lasted from June to October 2025. SciSci has made available working papers, issued periodically over the course of the project. Although these working papers are no longer up-to-date as SciSci begins real product-building, they offer a glimpse into the process through which a CPU design emerged from initial mathematical, code-theoretic, and computer engineering ideas.
Invention No. 6
Operand Table
>50,000 Exact Encodings for the Virtual Hensel I
Topics: FC-3-2025 encodings, Virtual Hensel I
Invention No. 4
Arithmetic Logic Units
A circuit-level description of how exact arithmetic is performed
Topics: Combinational logic, circuit design, carry addition, FC-2-2025 instruction computation, scalability, parallelization.
Invention No. 5
RIXA
Towards a RISC Instruction Set Architecture for Exact Computing
Topics: ARIXA assembly language, MRIXA machine code
Invention No. 2
The Virtual Hensel
The first emulation on the Hensel CPU architecture and a proof-of-principle of exact, 2-adic computing
Topics: χ-IDs and χ-address matching for distributed load-store, FC-3-2025 encoding for χ-IDs, loading operations, decompoundment and recompoundment of operands with respect to χ-IDs, algorithmic generation of FC-3-2025 encodings, hop calculus visualization, operand capacity scalability, arithmetic reach scalability, cost-savings of exact computing.
Invention No. 3
Load-Store Architecture
A circuit-level description of how operands are handled in the processor register cluster for efficient, exact arithmetic
Topics: LSU combinational logic, circuit tree design, relationship between χ-modification of operands by LSU loaders and Φ-perturbations of circuit tree paths, relationship to hop calculus and π-sequence passing, parallelization and scaling.
Invention No. 7
Arithmetic Verification
Checking Correctness of Virtual Hensel Arithmetic Logic Units
Topics: Virtual Hensel, FC-3-2025 encodings, 2AALUs, exact arithmetic, verification
Invention No. 1
Hensel CPU
An original computing architecture design for doing exact arithmetic, rather than floating-point
Topics: 2-adic expansions, FC 1-2025 standard for encoding 2-adic expansion coefficients, processor architecture, 2-adic arithmetic logical units (2AALUs), FC 2-2025 parallelized instruction standard, arithmetic parallelization, optimality of parallelization with respect to non-Archimedean distance, error-detection and fault-tolerance, supercomputing (i.e., zetascale) prospects and a exact operations per second (XOPS) benchmark.
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Early Developmental Timeline
